The problem
RISC-V is an open, fast-growing processor architecture, but it lacks the huge ecosystem of optimized libraries x86 accumulated over decades. Porting that code by hand is slow, delicate, and requires experts.
Code that translates itself
SARTECO 2026 · Research paper
How we taught a large language model to port vector libraries from x86 to RISC-V -and to fix its own mistakes- reaching up to 21.7× speedup on genomic alignment.
Porting the Striped Smith-Waterman Library to RISC-V via LLM-Driven Translation
The problem we accelerated
Sequence alignment with Smith-Waterman
Smith-Waterman finds the best overlap between two DNA sequences by filling this matrix and following the highest-scoring trail. It is exact but expensive: that is why it gets vectorized. It is exactly the library we accelerated.
QueryTGTTACGG
ReferenceGGTTGACTA
G
G
T
T
G
A
C
T
A
T
3
3
1
3
1
G
3
3
1
1
6
4
2
1
T
1
1
6
4
4
3
1
5
3
T
4
9
7
5
3
4
2
A
2
7
6
10
8
6
7
C
5
4
8
13
11
9
G
3
3
1
3
8
6
11
10
8
G
3
6
4
2
6
5
9
8
7
Optimal alignmentBest score: 13
GTT-AC
GTTGAC
Two phases, zero human intervention
From x86 intrinsic to RISC-V vector
Input · x86 SSE
__m128i r = _mm_add_epi16(a, b);Output · RISC-V Vector
vint16m1_t r = __riscv_vadd_vv_i16m1(a, b, vl);Compile-and-fix loop
compile
error
the AI fixes it
correct
Phase 1 · Correctness
Translates x86 intrinsics to RISC-V, using sse2rvv as a foundation. The goal: make it compile and return the exact same result.
Phase 2 · Optimization
Rewrites the code to exploit RVV's scalable vector-length model, squeezing out an extra 1.30× of speed.
The research in brief
Four ideas to understand the paper without being an expert.
The idea
What if a language model did the translation? We give it the x86 vector code and ask for its RISC-V equivalent, letting the compiler and simulator themselves flag when it gets it wrong.
How it works
A two-phase pipeline: the first guarantees the translation is correct; the second optimizes it. At every step, a compile-and-fix loop lets the AI iteratively repair its own errors.
Why it matters
The result matches a hand-optimized implementation in performance and correctness, but with no human intervention. It is a path to populate RISC-V with fast software far more quickly.
- peak speedup
- 21.7×
- extra in Phase 2
- 1.30×
- lines written by hand
- 0
Read the full paper
Published open access (CC-BY 4.0) at the XXXVI SARTECO 2026 conference. Code and data available.
DOI: 10.5281/zenodo.21064372